(1) Field of the Invention
The present invention relates to the field of microprocessor architecture and layout. Specifically, the present invention relates to the technology of clock signal distribution throughout a microprocessor device.
(2) Prior Art
Components of an integrated circuit operate based on the timing and pulsing of clock signals which provide a reference point or activation signal for circuit activity and processing. The clock signal also provides a timing or alignment reference which different circuits adopt when stepping through their respective processing tasks. It is important that the clocking signals be predictable and not delayed such that processing and execution by circuit components are accomplished in synchronization. Microprocessor integrated circuit devices utilize a system clock which provides timing and pulsing to drive the various elements and processing of the microprocessor. It is vital to the operation of a microprocessor that the system clock be supplied uniformly to all components of the microprocessor with minimal clock skew and minimal clock delay. Each system component should receive the same clock signal, in synchronization, with all other components.
Throughout the following discussions, reference is made to clock delay and clock skew. Clock delay refers to the timing delay between a clock signal within an integrated circuit to the system clock. Clock skew, on the other hand, refers to the variations between clock delays associated with various points of an integrated circuit. While it may be physically impossible to totally eliminate clock delay, it is not impossible to match this delay across the entire IC and thus eliminate clock skew to various circuit components. To this extent, two points within an integrated circuit may have equal clock delays, but no clock skew between them. Therefore, it would be advantageous to match clock delays for all circuit components and thus eliminate clock skew within an IC; the present invention offers such a solution.
As microprocessor integrated devices use faster and faster clock speeds, variations in the topology of the microprocessor device may introduce delay or error factors within the metal lines that carry and propagate the clock signal. As the clock signal pulse becomes narrower, these clock signal variations become significant in modern microprocessor design. These factors contribute to propagation errors within the clock signals and will act to delay the clock signals as they are distributed to the various components of the microprocessor. Resistance within the clock line and capacitance on the clock line will create RC skews as the clock signal propagates. Also, other discontinuities within the circuit topology of the microprocessor will add to the propagation error of the clock signal, such as differences in thickness of the components that surround the clock line which introduce variable dielectric values to the signal lines (such as dielectric thickness variations within the insulating layers). These dielectric variations will contribute to the capacitance of the clock signal lines. What is desired is a scheme to provide all components of the microprocessor with a synchronized and identical clock signal even in microprocessor architecture having complex topologies having complex dielectric variations across them.
Several prior art methods have been implemented in order to provide components of a microprocessor integrated device with a clock. FIG. 1A illustrates one such prior art method wherein a signal driver is used to supply a clock signal to all of the components of a microprocessor device. A microprocessor integrated circuit device 10 is illustrated such that its top metal processing layer is facing upward. Within this top metal layer is a connection point from a clock driver 12 which drives the microprocessor clock. The system clock is usually input from outside the chip by an oscillator network or circuit. The clock oscillator is then driven by the clock driver 12. The driver is coupled to a very wide line 14a which is then coupled throughout the microprocessor device in a tree or branch scheme as shown. Different components of the microprocessor will then couple to the branching structure at different points as needed to gain access to the supplied clock signal. As shown, the branchings of the tree 14b and 14c are less in width than the initial line 14a which is coupled directly to the driver 12. The line coupled directly to the driver must be wider in order to carry the entire clock signal throughout the components of the microprocessor device 10.
Because a single clock driver 12 is utilized by the prior art method of FIG. 1A to supply the entire chip, it must be a very high power driver, but this is not the only reason why this prior art technique utilizes a high current driver. It is desired to reduce the resistance of the line 14a by increasing its width to reduce to total RC component of the line. Resistance within the clock driver lines 14a, 14b, and 14c, is a function of the length of the signal line between a point and the driver. Signal skew is a function of the resistance and capacitance (RC) of the line. When the signal lines are relatively small, the proportional increase in line capacitance will not equal the proportional decrease in resistance upon widening the line 14a, therefore, the overall RC product will decrease upon widening 14a. However, by decreasing the resistance, the driver size must increase to supply additional current to the clock line. An increase of power is used to decrease clock skew. This high power driver may create an excessive amount of noise associated with the clock signal. Under this system, the signal lines 14a are widened to lower resistance, which requires relatively higher power clock drivers; all of the above done in an effort to reduce the signal skew.
Because the length of the signal lines are long in the prior art method of FIG. 1A, the skew associated with the clock signal of this method is very great and not predictable from component to component. In larger microprocessors, this skew can approach 1.0 nanosecond in degree. This is an unacceptable level of skew in modern computers that operate at speeds well in excess of 50 megahertz. Also, the variable width of the signal line (i.e., from very wide at 14a to smaller at 14c) contribute to more variable skew in the signal delivered throughout the microprocessor 10 depending on the length of the signal line. Therefore, this prior art technique requires a high power (and therefore noisy) clock driver and has a corresponding large amount of variable skew associated with the clock signal. What is needed is a clock distribution system that reduces the amount of skew within the clock signal supplied throughout the microprocessor without relying on high power drivers. The present invention offers such capability.
FIG. 1B illustrates another prior art clock supply implementation that utilizes several different current drivers 17a-17d which each receive the same clock signal input. The outputs of each driver are then coupled to a separate circuit block within the microprocessor. For example, driver 17a is coupled to block 15a, and 17b to block 15b and so on such that each block 15a-15d receives its clock signal by a separate driver of 17a-17d respectively. The widths of each of these lines are controlled such that they are constant. Also the length of each line is controlled such that each line has the same length. Since the components 15a-15d are located at different distances to the clock generators, the lines 18, 19, 20, and 21 are doubled back in some areas to maintain the constant distance. For example line 18 has a few double back running lines so that line 18 will be equal in length to line 19, etc. The line 20 has no doubling back and will determine the length for all the other clock lines. In so doing, the microprocessor device 10 of this design will deliver a clock signal to each component. This system is able to utilize lower power drivers 17a-17d because the lines are smaller and there are more separate lines to distribute the clock signal.
In theory this prior art design of FIG. 1B is workable but it offers several disadvantages. First, it may not be possible to maintain constant width for each of the lines 18-21 over the entire signal line from the clock drivers to the components. Also, each of the lines will cross over and under different circuit topologies of the microprocessor which will alter the effective capacitance of the overall line. Uncontrollable differences in the manufacture of the signal lines in the processing stages of the microprocessor will effect the thickness of the dielectric of these lines up to 20 percent which will effect the capacitance of these lines and therefore contribute to topological mismatch. Although these variations may exist within all designs, this prior art system does not account for them in the most advantageous manner.
In summary, it may not be possible to match the capacitance values and resistance values of the clock signal lines over the entire topology of the integrated microprocessor device 10. These variations in the resistance and capacitance of the clock signal lines 18-21 will create unwanted signal skew within the clock signals supplied to the components of the microprocessor. Therefore, differences in dielectric values and processing irregularities may render this prior art method unachievable. What is desired is a system that can supply a relatively constant and predictable clock signal to all of the components of a microprocessor regardless of topology and processing variations throughout the microprocessor device. The present invention offers such capability.
A third prior art design is illustrated in FIG. 1C. With this system, many clock drivers 21 are situated in the center strip of the microprocessor 10 and supply clock signals outward horizontally to the fight and left sides across the topology of the chip utilizing a horizontal signal line for each driver. The drivers 21 are distributed across the entire dimension of the microprocessor. The maximum length of each horizontal driver line is half the length of the microprocessor chip. Various circuit components 24 and 25 will tap into these clock signals where the drivers supply the illustrated horizontal clock signal lines. Each of the clock drivers are supplied with power via a power line 23 which is coupled to the outer portion of the chip where the power pads 28 are located. Each of the drivers 21 must be coupled to power. The initial clock signal is fed to the drivers 21 via the center strip of the microprocessor device 10. This prior art method is a distributed clock scheme.
The prior art method of FIG. 1C is disadvantageous because the clock drivers 21, and associated logic to initially bring the clocking signal to the drivers, will consume excessive amounts of circuit space within the center strip of the microprocessor. It would be advantageous to utilize this space (real estate) of the microprocessor for purposes other than just a clock supply function. Furthermore, because the drivers 21 are located far away from the power pads 28 of the chip (located on the edges), large power supply lines 23 must be incorporated into this design to supply the drivers 21 with power. The resistance associated with these high power lines create an excessive amount of noise within the overall microprocessor that becomes unacceptable at high processor operating speeds (more resistance yields more noise associated with the power line due to IR noise). Therefore, what is needed is a system for supplying a synchronized clock signal throughout a microprocessor that does not consume valuable circuit space (especially circuit space within the mid sections of the topology which is regarded at a premium) and also that does not generate an excessive amount of noise within the microprocessor. The present invention offers such advantageous functions.
Furthermore, regarding the clock distribution system, it would be advantageous to be able to interrupt the clock signal that supplies the microprocessor device. In certain applications, especially within laptop systems, it is advantageous to conserve power by reducing the clock pulses supplied to the microprocessor. Prior art systems have been developed that control the clock signal that supplies the entire microprocessor but not individual components within the microprocessor. However, it would be advantageous to be able to selectively control the application of the clock signal to various components of the microprocessor independently. It would be advantageous to be able to selectively interrupt the clock signal to some microprocessor components while allowing others to operate normally so as to perform power management functions within the microprocessor device. The present invention allows such capability.
Accordingly, it is an object of the present invention to offer a clock supply system to provide a synchronous clock signal throughout the components of a integrated microprocessor device with minimal signal skew and distortion. It is further an object of the present invention to provide a distributed clock system that does not consume valuable circuit space of the microprocessor that can be used for other advantageous purposes. It is further an object of the present invention to provide the above functions in a system that does not utilize relatively long high power lines and therefore that does not generate an excessive amount of signal noise associated with the clock signal. It is also a function of the present invention to provide the above in a system wherein the clock driver units of the distributed system can be individually disabled so that clocking signals can be temporarily suspended to individual circuit components of the microprocessor device for power management functions. These and other objects of the present invention not specifically mentioned herein will become clear upon review of the discussion of the present invention to follow.